The invention relates to a fully digital phase-locked loop realized by means of a digital signal processor and comprising a sampler followed by an analog-to-digital converter and a filtering ensemble connected to the input of a decision logic whose output controls said sampler.
Phase-locked loops are utilized in the widest telecommunication domains (e.g. in radio-locating) as well as in metrology (e.g. for frequency synthesis). The main characteristic feature of these loops is to permit synchronizing with a signal during noise-affected transmissions when the classical detection means are inoperable as a result of the weakness of the received signal. A digital phase-locked loop of the kind mentioned in the preamble is described in the article entitled "Digital Phase-Locked Loop Behavior with Clock and Sampler Quantization" by Carlos Polamaza-Raez and Clare D. McGillem, published in IEEE Trans. on Commun., Vol. COM-33, No. 8, August 1985, pages 753 to 759.
The loop according to the invention has been realized in a cryptophony equipment for ensuring at the receive end the synchronization of the sampling of the digital scrambled speech signal. In such a cryptophony equipment in which scrambling is effected by frequency sub-band permutation with the aid of digital processing, it is fundamental that at the receive end the exact synchronization of the samples is recovered.